HIGH VOLTAGE MODULE CONTROL
LOGIC
L. P. Dimitrov, B. B. Kunov
Institute for Nuclear
Research and Nuclear Energy
Sofia, Bulgaria
ludim@inrne.bas.bg
Abstract: The control logic of a 12 channel (HV) module
is described. It is implemented in two Xilinx XC9572 CPLD (master and slave).
The master is connected to a main controller via a bi-directional serial bus
and to the slave via inter-board serial connection. The master controls the
first group of six HV channels. The second group of the rest six channels is
controlled by the slave. The instructions issued by the main controller and
executed by the module are: enable/disable a selected (or all) channel(s);
write value to a selected (or all) channel(s); perform conversion of a selected
parameter, applied to an on-board serial ADC; read converted in the ADC value
and status of voltage and current protection registers; read status of an
interlock loop.
The HV module is the basic
unit of the HV Power Supply System for the muon chambers of the ME1/1 endcap
station in the CMS.
INTRODUCTION
High voltage (HV) power supply system [1] for the CMS
endcap muon stations ME1/1 [2,3] has been developed. The system of three
19’’-wide, 6U-high euro-mechanics /crates/ includes 216 HV channels. Every
crate houses one crate controller and six HV modules. The controllers are
connected to a MS-NT host computer via a serial RS-485 interface.
The HV module contains two printed circuit boards -
‘master’ and ‘slave’. On every board there is a group of six HV channels, with
its own hardware controlled voltage and current limit sources, and ‘interlock’
circuit, detecting disconnection of the HV multipin connector. A serial 12-bit
ADC on the master board is used to measure all of the monitored parameterss - the output as well as the limit voltages and
currents. Both boards have control logic - ‘master’ and ‘slave’ respectively.
The master logic is connected to the crate controller via a backplane
serial bus and to the slave logic via inter-board serial connection.
CONTROL LOGIC DESCRIPTION
The block diagram of the master control logic is shown on
Fig. 1. Three lines are used for data exchange between the controller and the
modules - bus clock /BCK/, bus data read /BDR/ and bus data write /BDW/. Four
address lines are used by the controller to address modules /MA0, MA1, MA2 and
ALL/. When ALL is true all modules are enabled for write operation /in this
case, the other address lines are ignored/. Other three address lines /LA0,
LA1, LA2/ determine local module address - it depends of the occupied position
in the crate. A status line /SLN/ informs modules whether instruction or data
are transmitted on the bus. In addition, master reset line /MRL/ initialises
all modules and channels.
Eight lines are needed to interconnect both slave and master
logic /and boards/ - slave clock /SCK/, slave data write /SDW/, slave write
enable /SWE/, slave instruction enable /SIE/, slave inhibit /SIH/, slave
interlock status /SIS/, slave voltage and current protection status /SVP and
SCP/.
Three lines are used to control the on-board ADC - ADC
chip select /ACS/, ADC clock /ACK/ and bi-directional data line /BDL/.
Eight lines are used to perform loading the HV channel
DACs. All DAC’s shift registers are loaded simultaneously by using DAC clock
/DCK/ and already mentioned above BDL lines. Then the data is transferred to
the output register of the addressed /or all/ DAC(s) depending of state on DAC
load lines /DL1 - DL6/.
Five lines are used to select a parameter to be applied
for measuring to the ADC - three address lines /MX0, MX1, MX2/ and two enable
lines /EN1, EN2/, which control two eight bit analog multiplexers.
Six lines disable/enable HV channels /CD1 - CD6/, twelve
lines are used to monitor channel voltage and current protection status /VP1 -
VP6 and CP1 - CP6/ and one line is used to monitor master interlock status
/MIS/.
One input line /CCE/ is used to select current protection
mode – “constant current” /CCF is true/ or “kill” /CCF is false/. The mode is
jumper adjustable.
The main blocks are described below:
MDDC - module address decoder. Its output MDS is true,
when the module is addressed /bus address is equal to local address/ or line
ALL is true.
ISRG - instruction register. This is 8-bit serial
register, where instruction itself is loaded before its execution. Generally it
contains four bit channel address /A0 - A3/ and 4 bits function code /A4 - A7/.
The ISRG is loaded when STL and MDS are true. In order to execute the
instruction, the STL is set false and the fixed number of clocks /depending of
the instruction/ is used by the controller. The instruction truth table is
shown on Table 1.
|
Instruction
code |
ALL |
Clk's Nbr |
Rd/ Wr |
Data |
Description |
|
A7 6
5 4 3
2 1 0 |
|||||
|
1 1 0 x x x x x |
x |
1 |
Wr |
|
Enable module
and load ID |
|
1 1 1 x x x x x |
x |
1 |
Wr |
|
Disable module and load ID |
|
0 1 1 0 c c c c |
x |
1 |
Wr |
|
Clear Prot. Rg(s) - channel
cccc |
|
0 1 1 1 x x x x |
x |
1 |
Wr |
|
Clear Prot. Rg(s) - all channels |
|
0 1
0 0 c c c c |
x |
1 |
Wr |
|
Set Prot. Rg(s) - channel cccc |
|
0 1
0 1 x x x x |
x |
1 |
Wr |
|
Set Prot. Rg(s) - all channels |
|
0 0 0 1
x x x x |
x |
16 |
Wr |
In |
Load all DAC’s shift registers |
|
0 0 1
0 c c c c |
x |
1 |
Wr |
|
Load DAC’s output rg - ch.
cccc |
|
0 0 1 1 x x x x |
x |
1 |
Wr |
|
Load all DAC’s output
registers |
|
1 0
x 0 c c c c |
1 |
15 |
Rd |
|
ADC conversion - ch. cccc (voltage) |
|
1 0
x 1 c c c c |
1 |
15 |
Rd |
|
ADC conversion - ch. cccc (current) |
|
1
0 x x x x x x |
0 |
14 |
Rd |
Out |
Read module
data register |
x - don't care
CHAD - channel address decoder. It controls the analog
multiplexers, thus providing correct parameter to be applied to the ADC.
CHSL - channel select logic. It selects addressed /A4 -
false/ or all /A4 - true/ channels. Therefore it is possible all channels to be
controlled simultaneously or individually.
FDEC - function decoding logic. Depending of the ISRG
content the asking function is allowed - load DAC output register /DLE/, load
DAC shift register /DCE/, read module data register /RME/, set/reset protection
registers /PRE/, start ADC conversion and transfer data to the module data
register /ACS/, set/reset inhibit register /OOE/.
CPRG - Channel protection registers. These registers are
controlled by protection lines /VP[1..6] and CP[1..6]/ as well as by the
controller. In case of over voltage, the channel is immediately switched off.
In case of over current, depending of CCE level the channel is switched off
/CCF false/ or the output current is kept to the limit level /CCF true/.
VPMX and CPMX - protection status multiplexers. On their
outputs /VPB and CPB/ status of the voltage and current protection registers of
the selected channels appears. If the channel on the slave board is selected,
then SVP and SCP inputs appear on the outputs.
SR14 - fourteen bit module data register. This register
contains data, which is read by the controller /from output BDR/. Different
modes can be performed. When OOE is true, the predetermined ID value is loaded
into the SR14. Thus the controller can recognise different types of modules
/different ID’s/. When ACS is true, the data from the ADC is transferred to the
least significant 12 bit of the SR14. In the same time the protection status
bits of the selected channel /VPB and CPB/ are loaded in the two free bits of
the SR14. When PRE is true, the data from the SR14 is transferred via the backplane bus to the controller. When limit voltages and
currents are processed instead of protections status the interlock levels are
transferred. This is performed by the slave board control logic.
1. L. Dimitrov, B. Kunov, I. Vankov. High voltage power supply system
for endcap muon station ME1/1 of the LHC CMS detector. Proc. of The ninth
scientific and applied science conf. “Electronics ET’2000”, book 2, p.75,
Sozopol, Bulgaria, Sept. 2000
2. CMS Muon Project. Technical Design Report. CERN/LHC 97-32,1997.
3. Proceeding of ME1/1 Engineering Design Report. CMS Document,
1999-47.